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Special Session 3: Advanced Memory and Computing-In-Memory Circuit Design
Introduction and Topics
Emerging data-centric applications, such as artificial intelligence, edge computing, and big data analytics, demand unprecedented energy efficiency and computational throughput. Traditional von Neumann architectures suffer from the well-known memory wall bottleneck, motivating the development of emerging memory technologies and computing-in-memory (CIM) paradigms. This special session focuses on the latest advances in memory devices, memory circuit design, and memory-centric computing, covering both conventional volatile memories (e.g., SRAM, DRAM) and non-volatile memories (e.g., Flash, MRAM, RRAM, PCM). The session invites contributions that address key challenges in high-performance memory design, including read/write stability, variability tolerance, offset cancellation techniques for sense amplifiers, refresh mechanisms for DRAM, and low-power circuit techniques. In addition, we encourage submissions on CIM circuit design reconfigurable in-memory computations.
Topics of interest include, but are not limited to:
- →High-performance SRAM, DRAM, Flash, MRAM, RRAM and other memory circuit designs
- →Offset cancellation and variation-tolerant techniques for memory peripherals
- →DRAM refresh optimization and row-hammer mitigation
- →Emerging memory-based CIM architecture and circuit designs
- →In-memory computing for AI accelerators and low-power edge devices
- →Novel memory cell structures and array architectures for CIM
Special Session Chairs
Chaoyue Zheng
Yangtze Delta Region Institute (Huzhou), UESTC | China
Assoc.Prof. Zheng Chaoyue is an Associate Researcher and Master's Supervisor at the Institute of Integrated Circuits and Systems, Yangtze Delta Region Institute (Huzhou), University of Electronic Science and Technology of China (UESTC). He has been recognized as a Class E High-Level Talent of Huzhou City. His research interests include neuromorphic devices and circuits, self-assembled monolayer interface modification, and in-memory computing chips for emergency signal processing. He has served as Principal Investigator of a Zhejiang Provincial Natural Science Foundation project, a Huzhou Municipal Natural Science Foundation project, a Young Leading Talent project, and three industry-funded projects. He has also participated in a National Natural Science Foundation of China General Program and a Provincial Natural Science Foundation Innovative Research Group project. Over the past five years, he has published more than 20 SCI papers, with 12 as first or corresponding author in prestigious journals including Small, ACS Applied Materials & Interfaces, IEEE Electron Device Letters, and IEEE Transactions on Electron Devices. He holds 19 national invention patent applications, 4 of which have been granted. Inspired by the locust lobula giant movement detector (LGMD) neuron, he has developed a flash-based in-memory computing chip with self-regulated neuron circuits, enabling low-latency emergency responses for unmanned vehicles while reducing dependency on CPUs and high-bandwidth data transmission.
Yue Zhao
Hefei Normal University | China
Dr. Zhao Yue received the Ph.D. degree in Microelectronics and Solid-State Electronics from Anhui University, Hefei, China, in 2024. She is currently a Lecturer and a Master's Supervisor in the School of Electronic Information and Integrated Circuits, Hefei Normal University, Hefei, China. Her research interests include high-performance static random-access memory (SRAM) and SRAM-based computing-in-memory (CIM) circuit designs. She has extensive experience in the complete IC design flow and has led or participated in multiple tape-out projects across 28 nm, 55 nm, and 65 nm technology nodes. She has published several papers in renowned journals, including the IEEE Journal of Solid-State Circuits (JSSC), IEEE Transactions on Very Large Scale Integration (VLSI) Systems, and Microelectronics Journal. Her work focuses on configurable in-memory computing architectures, offset cancellation techniques for SRAM sense amplifiers, in-memory Boolean logic operations and in-memory multiplication computing.
Contact
Conference Secretary: Ms. Joyce, Email: ieeeicsict@outlook.com
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