Search

X

Special Session 4: Chiplet-based Integrated Systems

Introduction and Topics

Chip vendors face significant challenges with the continued slowing down of Moore's Law and the end of Dennard scaling which increases the time between new technology nodes and thus skyrockets manufacturing costs for silicon. The slowing down of Moore's Law makes it increasingly difficult to integrate more transistors on a single chip. If transistor sizes stay constant, more transistors could be integrated via larger chips. However, larger chips are undesirable due to significantly higher manufacturing and verification costs. Manufacturing defects in high density integrated circuits can dramatically reduce the wafer yield. Lower yield translates into higher manufacturing cost.

As a promising design paradigm to solve the above challenge, in chiplet-based systems, multiple die/chiplets are integrated within the same package via advanced packaging technology such as a multi-chip module or silicon interposer. The chiplet architectures provide a variety of benefits that make them attractive, including lower cost, higher flexibility, and better sustainability. However, the design methodology should be studied to support efficient design of chiplet-based systems. In this special session, we will focus on the challenges of chiplet-based integrated systems and innovations to address these challenges.

Topics for this session include but not limited to:

  • →Advanced Packaging Technology
  • →Die-to-die Interface & Interconnect Technology
  • →Inter-Die Communication Network
  • →Chiplet-based Accelerator Design
  • →Chiplet-based Heterogeneous Systems
  • →Architecture & Design Space Exploration for Chiplet-based Systems
  • →EDA tools for Chiplet-based Systems
  • →Reliability, Testing, and Security for Chiplet-based Systems
  • →Physical Design for Chiplet-based Systems

Special Session Chairs

Xiaohang Wang
Prof.

Xiaohang Wang

Zhejiang University | China

Wang Xiaohang, professor of College of Computer Science & College of Cyberspace Security, Zhejiang University. His research interests cover computer architecture and system architecture optimization. He graduated from the Department of Information and Electronic Engineering, Zhejiang University, and previously taught at the School of Software Engineering, South China University of Technology.

He has authored over 70 papers published in top-tier journals including IEEE/ACM Transactions and flagship conferences such as DAC. He has received two Best Paper Awards from prestigious conferences in hardware design and hardware security, including VLSI-SoC. He has presided over more than 20 research projects, among which 6 are national-level programs: the Key Program, General Program and Youth Program of the National Natural Science Foundation of China (NSFC), the NSFC-Guangdong Joint Supercomputing Project, and Key R&D Projects funded by the Ministry of Science and Technology.

He has held multiple academic concurrent appointments: Session Organizer of NoCS 2018/2022; Vice Chair of the Organizing Committee of CCF DAC 2023; Member of the Steering Committee of NoCArc 2018; Session Chair of APCCAS 2018; TPC Member of ICCAD and CF (a CCF Rank B conference). He delivered an invited talk and served as Program Committee Chair at ICCS 2020, and gave invited speeches at sub-forums of the Annual CCF Conference on Fault-Tolerant Computing in 2020 and 2021.

Additionally, he has served as Guest Editor of journals including Mathematics (JCR Q1), Computers and Electrical Engineering, and Integration, the VLSI Journal, as well as Special Issue Editorial Board Member of Computer Technology and Development. He is also a member of the Fault-Tolerant Computing Technical Committee and the Integrated Circuit Technical Committee of the China Computer Federation (CCF).

Letian Huang
Assoc. Prof.

Letian Huang

UESTC Yangtze Delta Region Institute | China

Letian Huang is the associate professor of University of Electronic Science and Technology of China (UESTC); Deputy Director of the Research Center for Integrated Circuits and Systems, Yangtze Delta Research Institute (Huzhou), UESTC.

He obtained his Bachelor’s, Master’s and Doctoral degrees from the University of Electronic Science and Technology of China. From September 2013 to September 2014, he worked as a visiting scholar at the Department of Electronic Systems, KTH Royal Institute of Technology, Sweden.

He currently serves as Director of the Southwest University Association for Electronic Technology and Electronic Circuits, Member of the Embedded System Technical Committee and Member of the Integrated Circuit Design Professional Group of the China Computer Federation (CCF), as well as Chair of the Chengdu Chapter, IEEE Council on Electronic Design Automation. He has been invited to hold positions such as General Chair and Technical Program Chair for numerous international conferences.

He has been awarded the title of Outstanding Instructor for multiple editions of the National Graduate Electronic Design Competition and honored as Online Distinguished Teacher of UESTC. His research focuses on the interdisciplinary area of computer system architecture and chip design. He has conducted in-depth research on System-on-Chip (SoC), microprocessor design, hardware-software co-design, as well as system-level design for testability and test methodology of integrated circuits.

Contact

Conference Secretary: Ms. Joyce, Email: ieeeicsict@outlook.com

Copyright © 2026