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Tutorial Session 03
Breaking the AI-Computing Driven Interconnect Bottleneck
Date: October 27, 2026 | Time: 14:00 - 17:00
Speakers
Prof. Yukui Yu
Xidian University, China
Talk Title: High-Speed SerDes for AI Interconnects: Scaling Toward 224G/lane
Bio.: Yukui Yu is currently a Professor and Ph.D. advisor at Xidian University. He received the Ph.D. degree from Harbin Engineering University, Harbin, China, in 2018. From 2018 to 2020, he was a Postdoctoral Fellow with KAIST, South Korea. In 2021, he joined Huawei Hisilicon Semiconductor, Shenzhen, China, as a Principal Engineer. His research focuses on oDSP and SerDes.
Assoc. Prof. Yuan Du
Nanjing University, China
Talk Title: High-speed Parallel Interconnects: Crosstalk Cancellation Techniques
Bio.: Yuan Du received B.S. degree with honor from Southeast University (SEU), and Ph.D. degree both from University of California, Los Angeles (UCLA). Since 2019, he has been with Nanjing University, Nanjing, China, as an Associate Professor. His current research interests include designs of high-speed inter-chip/intra-chip interconnect circuits, RFICs, and machine-learning hardware accelerators. He was the recipient of the Microsoft Research Asia Young Fellow (2008), Southeast University Chancellor’s Award (2009), Broadcom Fellow (2015), and IEEE Circuits and Systems Society Darlington Best Paper Award (2021).
Abstract
The explosive growth of generative AI and large language models (LLMs) has created an unprecedented compute-interconnect co-design challenge. As AI accelerators scale to tens of thousands of chips per cluster, data movement has surpassed computation as the dominant consumer of power and the primary limiter of system performance. This tutorial addresses the critical interconnect technologies that enable next-generation AI computing: the scaling of serial links toward 224Gbps per lane and advanced crosstalk cancellation techniques for high-density parallel interfaces. We will present fundamental physical limits, state-of-the-art circuit architectures, and emerging solutions from leading industry and academic groups. Special emphasis will be placed on how interconnect design is evolving to meet the unique requirements of AI computing workloads, including low latency, high energy efficiency, and massive bandwidth density. Attendees will gain deep insights into the cross-layer design tradeoffs spanning circuits, packaging, and system architecture that are shaping the future of computing systems. This tutorial is intended for circuit designers, system architects, and researchers working in high-speed communication, VLSI design, and AI hardware acceleration.
Schedule
- Talk 1: High-Speed SerDes for AI Computing Interconnects: Scaling Toward 224G/lane (By Prof. Yukui Yu)
- Talk 2: High-Speed Parallel Interconnects for Accelerated Computing: Crosstalk Cancellation Techniques (By Assoc. Prof. Yuan Du)
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